Computer shift control circuits



Aug. 21, 1962 Original Filed March 4, 1955 MU DV iew TO 207 ACCUMULATORS a FIGI ADI

-DDI

SIGN TIM AR-l DDI

DlGlT TIME AR-O G. G. HOBERG ETAL COMPUTER SHIFT CONTROL CIRCUITS 5Sheets-Sheet 1 LSD I SIGN :opa low I DPS I DPS I 0P4 0P3 l 0P2 DPI UPC 61 e l.234567890|2 DPIZ DPII DPIO 0P9 MSD [NVENTORS- GEORGE G. HOBERGATTORNEY Aug. 21, 1962 G. e. HOBERG ETAL 3,050,717

COMPUTER SHIFT CONTROL CIRCUITS Original Filed March 4, 1955 5Sheets-Sheet 2 :2 E SHIFT E CONTROL LEFT SHIFT RIGHT NO 275 SHIFT SHIFTOTHER STATES 273 V M mews LONG DELAY 1" 22| B DIGITS LONG GEORGE G.HOBERG JOHN R.VAN ANDEL B EDWARD w. VEITCH ATTORNEY 1962 G. G. HOBERGETAL 3,050,717

COMPUTER SHIFT CONTROL CIRCUITS 5 Sheets-Sheet 3 Original Filed March 4,1955 v Emfiwmm 296M550 .Tma 2 E1565 TH EEG 1.2m .rEIm FIG-m RIGHT SHIFTNNN IEE Firm 02 1.2a Fuiw hum INVENTORS. GEORGE G. HOBERG JOHN R. VANANDEL BY EDWARD W. VEITCH 6 3 YEA ATTORNEY Aug. 21, 1962 G. G. HOBERGETAL 3,050,717

COMPUTER SHIFT CONTROL CIRCUITS O riginaI Filed March 4, 1955 5Sheets-Sheet 4 5A w TIMING PULSES 3 DRUM TRACKS) Tlllllllilllllmlllllllllllll llllllfilmllillllllll Illilll H GEJJJSEC -HH-ISOUSEC a 9 n WBC H-I7OOLISEC-H lspssc MAGNIFID VIEWS RAW TlmnTePULSES BLLSEC T 9 o 2 3 4 5 e 1 s 9 o 1 1300 RAW "T PU LSES PER DRUM REVasussc I3OJJSEC o: (m (E) (om/Wm I30 PAIRS PER DRUM REV was (WJUKB) (ONEPAIR OF 'wa"|=u| ses LIKE nus), l 12 PULSES PER DRUM REV TYPES g DERIVEDPULSES TRIGGER PULSES (IBOOLISOOU ZSOOHU PER REV) "U +msEc u H fl H H HH H H H H [1 [1 +wszc s oo||223344 s-es11a OOI oaum wnrrms PULSES usooPER REV.) I.5)JSEC w s o l 2 a 4 5 s 1 e s o I an PULSES I300 PER new pp T 9 o 1 z a 4 5 s 1 a 9 o I4- zpssc u H0 H1 H2 H5 H4 H5 H6 H H H9 H0SAMPLER OR CHOPPER PULSES (2600 PER REV.) F H men PULSES usomaos PERREV.) +1 papssc D=DE-T0E}1 H FIG.4

INVENTORS. GEORGE G. HOBERG JOHN R. VAN ANDEL BY {EDWARD W.

ATTORNEY United States Patent 3,050,717 COMPUTER SHIFT CONTROL CIRCUITSGeorge G. Hoberg, Berwyn, John R. Van Andel, Bridgeport, and Edward W.Veitch, Rosemont, Pa., assignors to Burroughs Corporation, Detroit,Mich., a corporation of Michigan Original application Mar. 4, 1955, Ser.No. 492,062. Di-

vided and this application Aug. 7, 1956, Ser. No. 602,654

Claims. (Cl. 340-1741) This application is divided from the co-pendingUnited States application for patent entitled Electronic ComputerSystem, S.N. 492,062, filed March 4, 1955. This invention relates todata storage systems useful in electronic computers, and moreparticularly to control circuits for shifting significant digits ofarithmetic information in data storage and processing circuits.

In data storage systems including cyclic memory devices such as amagnetic drum, information is frequently stored in circulating circuitloops or revolvers including storage areas on the drum surface. Inarithmetic systems of electronic computers such revolvers are frequentlyused as registers for retaining numbers which are used during certainarithmetic operations. In many of these arithmetic operations, such asmultiplication, it becomes necessary to shift the position ofsignificant digits such as decimal characters. Revolver systems areparticularly advantageous in performing such shifting operations, asoutlined in the U.S. Patent No. 2,716,159, issued to T. H. Flowers onAugust 23, 1955, and the Great Britain patent specification No. 727,926,published April 13, 1955. These patents indicate the manner of shiftingdata by introducing delay means in revolver systems for causing dataprecession when shifting is desired.

Certain problems, however, exist in attaining successful operation ofmagnetic drum revolver systems including selective alteration of dataand incorporating delay circuits because of critical timing necessary towrite signals exactly in the same position previously recorded dataoccupies. Thus, the spacing of heads along the record track must beadjusted to encompass, together with data in transit in the couplingcircuits, an exact integral number of recorded spots. This operation isvery costly since it must take place for every revolver track in view ofslight changes in system delays and timing signal spacing on the record.Accordingly it is highly desirable to provide a system requiring only asingle head adjustment. The provision of more than two heads in a.revolver track may not be tolerated therefore since they requireextremely careful alignment in all permutations and combinations ofcircuit paths and head adjustments. Furthermore, system timing must takeinto account and correct certain discrepancies such as may be introducedby changes of temperature or momentary changes in cyclic record speed.

Accordingly it is an object of the invention to provide improvedrevolver systems, which are capable of shifting the significantpositions of recorded data signals.

It is another object of the invention to provide a revolver systemoperable with selective alteration techniques.

A further object of the invention is to provide improved and simplifieddata processing and control circuits useful in electronic computers.

In accordance with the invention, therefore, there is provided amagnetic drum revolver system operable to shift the significant positionof recorded data in either direction in response to simplified controlsignals. In order to provide an economically feasible system, therevolver track employs a single read and write head spaced apart anintegral number of recording spots along the track. Special timing andpulse shaping circuits are provided in order to permit select-ionalteration of previously recorded data even when the signal processingcircuits contained in the revolver loop external to the drum aresubjected to variations in signal delay.

The following description of the invention and its organization willpoint out in detail the foregoing and further features of advantage,particularly when considered with reference to the accompanyingdrawings, in which:

FIG. 1 is a logical schematic diagram of a magnetic drum read-writecircuit illustrating the operation of the present invention;

FIG. 2 is a logical schematic diagram of a shift control circuitembodiment of the invention employing a revolving data processing loop;

FIG. 3 is a logical schematic diagram of a shift control and accumulatorcircuit of the invention;

FIG. 4 is a waveform chart illustrating timing pulse relationships asutilized in accordance with the teachings of the invention; and

FIG. 5 is a logical schematic diagram of a timing signal processingsystem which may be used in accordance with the invention.

In the rotating magnetic memory unit of FIG. 1, each data word hastwelve decimal digits plus sign and is stored in serial form so that thesign may be read first and then the least significant digit, etc.

Each digit is stored in pulse-count form with 10 memory bit cellsallocated for each digit. One of the bit cells termed a spacer cell islocated between two successive digits and is not used for informationstorage. Since the digit zero requires no bits, the digits from zerothrough nine need only the remaining nine of the ten available bitcells.

A typical cyclically movable or rotating memory device is the magneticdrum 51, which is diagrammatically shown with associated word sectors 0to 9. This magetic drum when rotated at about 3600 r.p.m. provides amaximum access time for one track revolution of about seventeenmilliseconds. Thus, the maximum access time for one of ten similar wordsstored in equidistant peripheral arcs or sectors around one track isabout one and seven tenths milliseconds. The data memory may compriseseveral drum memory tracks, each storing ten words in the mannerdisplayed by waveform 202.

The drum is provided with an accumulator A register (A REG.) track shownin FIG. 5. The A REG. comprises a one word track located in a singlesector, connected with an accumulator loop for re-entry of informationwhich provides a maximum access time of about one and seven tenthsmilli-seconds from the start of the recirculating word. This track isconnected in the accumulator loop to serve as an accumulator register inthe manner illustrated schematically by FIGURES 2 and 3.

As shown in FIG. 5, three separate timing tracks are provided in thememory timing section on the drum for the bit, word, digit and rotationtiming pulses. There are 1300 bit timing pulses on the basic track thusserving to produce a 78 kilocycle basic computer operating frequency.This provides for ten words of twelve decimal digits plus sign in thepulse-count notation on each track. The WBC track produces ten Wordspulses W and one each B and C rotation pulses, which are distinguishedin the manner shown in the timing chart explained hereinafter inconnection with FIGS. 4 and 5. The DE timing track provides digit pulsepairs for each drum rotation. The timing signals are passed from thedrum timing track section through read and write circuits to thecomputer timing circuits which are used to synchronize operations bygating signals at local circuit positions throughout the computer.

For translation of data between the rotating memory and other computerunits all data is processed through suitable read and write controlcircuits to the accumulator of FIGURES 2 and 3. The accumulatorprincipally comprises a serial pulse-count adder circuit 222, which iscoupled in a loop circuit with the A register memory track through theshifting circuits and a writing head.

All of the arithmetic operations are timed by means of signals derivedfrom stored timing signals in the memory section of the drum andprocessed in the timing circuits of FIG. 5. The corresponding waveformsare illustrated in FIG. 4 and detailed schematic circuits are found inthe above mentioned co-pending application. The block diagram circuitsof FIG. 5 are discussed hereinafter together with timing pulsecharacteristics of both the raw recorded pulses and those timing pulsesderived therefrom as indicated by the waveforms of FIG. 4.

The basic timing track has 1300 raw timing pulses T spaced at thirteenmicrosecond intervals which are used to derive pulses for synchronousoperation of the computer at bit frequencies of either 78,000, or156,000 cycles per second. The raw timing pulses T are used in the basictiming section 130 for deriving a series of shaped pulses t, u, tvu, T,U, TvU, and w. The timing and widths of these pulses, together with anindication of the timing of the decimal pulses count notation in thecomputer system are seen in the waveforms of FIG. 4. From thecorresponding letter notation at the output leads of the basic timingsection 130 each timing signal may be traced back to the basic timingtrack through the processing circuits.

Thus, the raw basic timing pulses T at input terminal W are fed throughthe two stage tuned amplifier circuit 134 to produce a sine wave outputsignal at terminal C. Shaping of the sine wave signal at terminal C isperformed by overdriving a biased triode amplifier 132 in a circuitproviding lowered plate potential. This eifectively converts the sinewave output signal of the intermediate tuned amplifier 134 to a shapedWave at the output terminal Y of the overdriven shaping amplifier 132,from which is derived in further circuits the one microsecond wide and upulses of FIG. 4.

The shaped wave at terminal Y is further processed in a pentodeamplifier tube 136 which serves as a further peaking circuit to produceat the output terminal K the t timing pulse. The peaking is done in adamped resonant pulse forming circuit.

To form the u timing pulse at terminal L, an inverter circuit comprisingthe triode amplifier 140 amplifies the reverse half of the sine wavefrom terminal Y to produce an input signal to a similar peaking circuit136 to produce at the output terminal L the shaped u timing waveform.Thus, by utilizing the reverse half cycle of the available shaped sinewave from terminal C, the t and u clock pulses are caused to beinterspersed with each other, as shown in FIG. 4.

The 1.5 microsecond w drum writing signal is derived also from the 13microsecond sine wave signal at terminal C (FIG. 5). The input circuitof the overdriven amplifier 132 in the v signal processing circuit isshaped by means of a suitable phase advancing circuit 146 which causesthe w timing pulse to have a leading edge starting one-half of amicrosecond before the corresponding t pulses. The damped resonant pulseforming circuit is tuned to produce a one and a half microsecond pulse.Thus, the w pulses last for a duration of one and a half microseconds,and are therefore suitable for actuating circuits for writing upon themagnetic drum. In the computer system, these wider writing pulses permitsynchronous ret-iming of gated pulses read from the drum. The peakerstage 136 further shapes the v waveform to produce output pulses w atterminal M.

The further two microsecond wide clock pulses T and U are derived fromthe sine wave produced at the input terminal C. A cathode followercircuit 144 couples the sine wave signal to two separate processingchannels for the respective clock pulses T' and U. An inverter circuitserves to intersperse the U pulses with the T pulses by utilizing adifferent half cycle of the sine wave input signal. By means of theinterspersed phase advancing circuits 146, the sine wave signal iscaused to trigger oil the overdriven amplifiers 132 soon enough to causethe T and U pulses to be derived for two microseconds of which the latermicrosecond correspondswith the I and a trigger pulses. The pulses arefinally shaped in the peaker circuits 136 to produce at the respectiveoutput terminals X and the shaped T and U pulses.

Some of those circuits described in connection with the basic timingprocessing circuits are likewise used for processing the other timingtrack and data track signals in sections 150, 152 and 178 of FIG. 5. Adiiferentiating amplifier 148 is used in the memory reading stage of theamplifier circuits in reading sections 150, 152 and 178. The pulses arethen shaped in the overdriven amplifier to produce output signals.

These shaped signals are further processed through the pulse amplifiercircuit as are the signals derived from the basic timing track asindicated in the pulse amplifier circuit portion 161.

Other various combinations of timing pulses which are necessary atdifierent stages of the computer for proper operation are derived in theand circuits of. the processing section 176 of FIG. 5. Since digitalinformation is handled as pulses throughout the computer system, thedata tracks also derive similar shaped pulses in the data section 178.

The drum read-Write circuits are shown for the three separate datasections of the magnetic drum. These sec tions, namely, the memory ordata tracks, the A register loop and the B register track each haveprovisions for reading and writing magnetic information upon the drum.In each of the three data sections similar read and write amplifiers areutilized for writing alternatively 1s and Os. Since the A registercircuit shown in FIGURES 2 and 3 comprises a circulating loop forre-entry of information upon the same memory track after suitablemodification, a separate reading head 219 is spaced a fixed distance ofabout one computer word from the loop writing head 220. However, in theB register and memory sections the same magnetic head winding is usedboth as a reading and writing head. A single read head and a singlewrite head are coupled with the separate reading and writing circuits ofthe A register loop. As shown in FIG. 2, the interspersed shiftingcircuits permit information written on the drum to be shifted in onecomplete Word cycle from a position labelled starting time to theposition labelled termination time. Thus a shift of one digit to theleft is illustrated, and similarly no shift and right shift operationsmay take place.

The organization of the data upon tracks of the drum is shown for the Bregister in the logical diagram of FIG. 1 and appear the same for thedata tracks. A typical word as stored upon each drum sector is indicatedby the waveform 202. This waveform typifies the words stored and usedthroughout the computer. As the drum rotates, the first decimal digitDPO, which represents the sign, is presented in each sector. The sign isrepresented by nine 1 pulses for negative sign and nine 0 signals for apositive sign. In general, a return to negative signal may be used andthereby the negative level or absence of pulse represents a 0 signal.

Between each decimal digit of nine recorded bits is a guard cell so thatten complete recording bit spaces are assigned to each decimal number.Next in succession after the sign digit DPO is the least significantdigit DP1 of the recorded Word, which in this illustrative case is a twoand is represented therefore by two pulses in the pulse count notationused throughout the system. Each decimal digit is then read insuccession until the most significant digit DP12 is reached. For allcomputations the decimal point is fixed between the most 5 significantdigit DP12 and the next lower significant digit DP11. Thus, in the Bregister track of the drum, the same word would be written in all tensectors a maximum therefore would be available at the reading head 188FIG. 1 with an access time of approximately 1.7 milliseconds for a drumrevolution of 3680 rpm.

Signals to and from the transducing head 188 (FIG. 1) are processed inthe read-write circuit section 264 in the manner hereinbefore describedwith regard to FIG. 5 and in greater detail in the aforementionedcopending application, Serial No. 492,062, assigned to the same assigneeas the present invention. Separate output signals for both 0 and 1recorded information, as indicated by the notation BR-O and BR-l go tothe accumulator adder register 222, FIG. 3, from the shown memoryregister, the B register. Since the B register is read only duringmultiplication or division, the or circuit 205, FIG. 1, produces signalsderived from the computer instructions for actuating the output gatingcircuits 206 and 207. Coincidence of the multiply or divide instructionwith information BRl or BR0 on the B register and clock pulses -DE.Uproduce corresponding output signals which are sent to the accumulator.Therefore, during the receipt of clock pulses -DE.U, shown in FIG. 4,which occur during presentation of each of the recorded sectors of the Bregister, any recorded B register information is read out into theaccumulator in response to a multiply or divide signal received at theinput or circuit 245.

The accumulator register together with the accompanying shiftingcircuits is shown in logical form in FIG. 2 to indicate the manner ofcirculation and modification of information picked up at the readinghead 219 and rewritten at one recording position by the single writinghead 220. Each word as stored in the entire accumulator loop has 12decimal digits plus a sign compartment. During regeneration of theinformation the word sign is stored in a flip flop circuit to leave thesign compartment blank. During normal circulation one of the thirteendigits is stored in the control circuit path which includes delay means222 for normal no-shift operation, and the other twelve are recorded onthe drum surface located between the read and write heads 219 and 220.The provision for storage of one digit in a decimal counter delay line222 in the control circuits enables precession of information about theaccumulator loop. This provides the shift right operation when directcoupling bypasses the one digid delay. An additional delay line 222 ofone digit in a further decimal counter may be incorporated in analternate control circuit path which includes delay means 221 enablesshift left sequencing. The result of the left shift operation isindicated in FIG. 2 by the comparison of the two words located betweenthe read heads at the starting and termination of one shift period. Thenormal accumulator circulation path is from the read head 212 throughthe normal one digit delay circuit 222 through the no-shift path andback to the write head 22% as controlled by a no-shift input instructionthrough the or circuit 273. The no-shift signal is derived from computercircuit logic in response to various input conditions at the or circuit273, as described in the copending application hereinbefore mentioned.

During precession, automatic entry of zeros may take place without extraequipment because of the previous recording of Os or the blank in thesign compartment. This in the sine position may be recorded in thelowest order digit (DPl) during the shift left operation since the delayline 222 holds the digit in position (DPl) and the delay line 221 holdsthe sign digit in position 0 (DPO) at starting time of each word. Thusby selecting sequentially the no shift path and the left shift path fora left shift operation, the zero digit position (DPO) is stored in twosuccessive positions at termination time representing zeros in the leastsignificant digit and sign 6 pulse positions. Likewise in connectionwith the right shift operation the zero digit position (DPO) willreplace the most significant digit position (DPl2) As seen from thewaveforms of FIG. 4, the drum writing pulses w are formed with a leadingedge occurring before that of the corresponding clock pulses t. Thisoverlap retiming serves the purpose in the shift control circuits ofFIG. 2 of making the regenerative drum loop head spacing and circuitdelay configuration less critical. Should the data be recirculatedWithout retiming, even a very small change in timing caused by eitheradvancing or delaying the pulses in any of the three optional circuitloops might cause enough precession or mistiming to be built up to causeerroneous circuit operation, especially when transferring signals fromone circuit path to another. Thus, the longer drum writing pulsesoverlap signals from the reading head 219 to produce a wide enoughsignal to be gated precisely at the desired time so that, if the headsare accurately spaced, small variations of timing in the three circuitsin either direction will be corrected by the retiming action. Either adelay or advance of pulse timing may be caused by misplacement of theheads. Normally some delay is caused in electrical interconnectingcircuits causing pulse timing to be slightly retarded. By causing theleading edge of the w pulses to occur prior to the timing pulses t, thetiming variation tolerance in the shift paths even may be advanced andoperation of the regenerative shift control circuits thus is madereliable during either delay or advance without the necessity for strictcustom adjustments of delay lines in the respective circuit paths.

In FIG. 3, the entire accumulator loop is denoted together with an addercircuit and its plurality of input conditions as described in the abovementioned copending application, and which is not herein described indetail since the various input signal considerations are not necessaryto an understanding of the present invention. In this circuit the adder27 presents the necessary one digit delay required in the no-shift path.

Having therefore disclosed hereinbefore features not heretofore known inthe art, the appended claims are directed to those features of noveltybelieved to define the nature of the present invention.

What is claimed is:

1. In a magnetic drum shift register device, two single transducer headsmounted in spaced apart relation adjacent to the periphery of said drum,three separate loops each providing a selectable regenerative pathconnectible between said transducer heads comprising respectively a leftshift path, a right shift path and a no shift path, and control gatingmeans for selecting one of said regenerative paths between saidtransducer heads whereby shifting operations are performed.

2. In a data recording apparatus, shift control circuits comprising arevolving memory loop having a magnetic memory data track and two singletransducer heads spaced apart along the track substantially the numberof digits to be recorded in the loop, three separate circuit loopsproviding respectively: a first circuit path connectible between saidheads, a second circuit path connectible between said heads andproviding delay wherein said second path and said magnetic memory datatrack together provide delay for all digits to be recorded, a thirdcircuit path connectible between said heads and providing greater delaythan said second path, and control means for selecting one of said threecircuit paths whereby shifting operations are performed.

3. In an electronic computer system, a revolving memory loop on a movingmagnetizable medium, a transducer head for reading from said loop, atransducer head for writing on said loop, three separate loop circuitseach providing a separate regenerative path connectible between saidread transducer head and said write transducer head comprisingrespectively left shift, right shift and no shift paths, shift controlcircuits connected in said loop circuits and responsive to signals fromthe computer system for connecting a selected one of said paths to theheads whereby information received by the write head from the read headis selectively shifted or not shifted depending upon the regenerativepath selected.

4. In an electronic computer system, a revolving memory lane on a movingmagnetizable medium, a single reading means for reproducing signals fromdata stored in said lane of the magnetizable medium, a single writingmeans for introducing data onto said magnetizable medium regenerativelyrecording signals read from said memory lane, three separate andoptionally selectable data processing circuits each having a diiferenttime delay, control circuit means for selecting one of said dataprocessing circuits and coupling the same between said reading andwriting means for precessing data on said revolving memory lane.

5. In a data storage apparatus, a movable member having a magnetizablesurface, two single transducer heads spaced apart and adjacent to saidsurface, three separate loop circuits each including a separateregenerative path connectible between said transducer heads comprisingrespectively left shift, right shift and no shift paths, and shiftcontrol circuit means for coupling one of said regenerative pathsbetween said transducer heads forming a regenerative closed loop wherebyshifting operations are accomplished.

6. In an electronic computer system, a revolving memory loop on a movingmagnetizable medium, a transducer head for non destructive reading fromsaid loop, a transducer head for destructive writing over informationformerly written on said loop, three separate circuit loops eachproviding a separate regenerative path connectible between said readtransducer head and said write transducer head comprising respectivelyleft shift, right shift and no shift'paths, shift control circuitsconnected in said circuit loops and responsive to signals from thecomputer system for connecting a selected one of said paths to the headswhereby information received by the write head from the read head isselectively shifted or not shifted depending upon the regenerative pathselected.

7. In an electronic computer system, a revolving memory loop on a movingmagnetizable medium for storing a fixed number of digits, a transducerhead for reading from said loop, a regeneration transducer head forwriting on said loop, three separate loop circuits each providing aseparate regenerative path connectible between said read transducer headand said write transducer head in series with said memory loop, saidfirst path comprising means for delaying at least a single digit, saidsecond path comprising means for delaying at least two digits, and saidthird path comprising means for delaying no digits, and shift controlcircuit means connected to said regenerative paths and responsive tosignals from the computer system for connecting a selected one of saidpaths to the heads whereby information read by said read head may berouted through different ones of said paths and the time required forregeneration may be selectively varied.

8. In an electronic computer system, a revolving 8 memory loop on amovable magnetizable medium for serially recording a word having aplurality of digits, a transducer head for reading from said loop, a'transducer head for writing on said loop, three separate circuit loopseach including a separate regenerative path connectible.

between said read transducer head and said write trans ducer head,including respectively a path having delay means equivalent to one digittime, a path having delay means equivalent to two digit times and a pathhaving no delay means, each of said delay means including a decadecounter for serial read-in and serial read-out, and shift controlcircuit means connected to said regenerative paths and responsive tosignals from the computer system for a selected one of said paths to theheads whereby information received by the write head from the read headis selectively delayed or not delayed, depending upon the regenerativepath selected.

9. In an electronic computer system, a revolving memory loop on a movingmagnetizable medium for serially recording a word having N number ofdigits, a transducer head for reading from said loop, a transducer headfor writing on said loop, said heads being spaced apart from each othera distance equivalent to N'l digits, three separate circuit loops eachproviding a separate regenerative path connectible between said readtransducer head and said write transducer head, including respectively apath having no time delay, a path with delay means having a time delayequivalent to one digit and a path with delay means having a time delayequivalent to two digits, said time delay means including an addercounter for serial read-in and serial read-out, timing signals ofdiscrete width synchronized with said revolvingmemory loop and occurringsimultaneously with said words for retiming digits introduced by saidwriting transducer head, and shift control circuit means connected .tosaid regenerative paths and responsive to signals from the computersystem for connecting a selected one of said paths to the heads wherebyinformation received by the write head from the read head is selectivelydelayed or not delayed, depending upon the regenerative path se-vlected.

10. The combination defined in claim 7 wherein each of said means [fordelaying includes flip-flop cascade counters for serial read-in andserial read-out.

References Cited in the file of this patent UNITED STATES PATENTS2,609,143 Stibitz Sept. 2, 1952 2,716,159 Flowers Aug. 23, 19552,718,356 Burrell et \al. Sept; 20, 1955 2,729,809 Hester Jan. 3, 19562,770,797 Hamilton et al Nov. 13, 1956 2,793,344 Reynolds May 21, 19572,845,609 Newman July 29, 1958 2,954,166 Eckdahl Sept. 27, 1960 FOREIGNPATENTS 1,084,147 France June 30, 1954 749,836 Great Britain June 6,1956

